1. Field of the Invention
The present invention relates to test devices, and more particularly, to a test device for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors, as well as a test method thereof.
2. Description of the Related Art
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are presently produced based on different objectives, making DRAM an important semiconductor device in the information and electronics industry.
Most DRAM carries one transistor and one capacitor in a single DRAM cell. The memory capacity of the DRAM can reach 256 MB. Therefore, with increased integration it is necessary to reduce the size of memory cells and transistors to accommodate DRAM with higher memory capacity and processing speed. A 3-D capacitor structure can reduce the occupied area on the semiconductor substrate, such as with a deep trench capacitor, and is applicable to the fabrication of the DRAM with capacity of 64 MB and above.
As compared with a traditional plane transistor, however, this structure covers many areas of the semiconductor substrate and cannot satisfy the demands of high integration. Therefore, a vertical transistor which can save space is important in structuring a memory unit.
The adjacent memory cells may experience current leakage and cell failure, reducing process yield, if active area masks and memory cell structures are not aligned accurately. Therefore, process yield and reliability of the memory cells can be improved if alignment accuracy between the masks of active areas and memory cell structures is controlled within an acceptable range.